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<0.5 cmos, 1.65 v to 3.6 v, quad spst switches adg811/adg812/adg813 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2009 analog devices, inc. all rights reserved. features 0.5 typical on resistance 0.8 maximum on resistance at 125c 1.65 v to 3.6 v operation automotive temperature range: ?40c to +125c high current carrying capability: 300 ma continuous rail-to-rail switching operation fast switching times: <25 ns typical power consumption <0.1 w applications cellular phones mp3 players power routing battery-powered systems pcmcia cards modems audio and video signal routing communications systems general description the adg811/adg812/adg813 are low voltage cmos devices containing four independently selectable switches. these switches offer ultralow on resistance of less than 0.8 over the full temperature range. the digital inputs can handle 1.8 v logic with a 2.7 v to 3.6 v supply. these devices contain four independent single-pole/single- throw (spst) switches. the adg811 and adg812 differ only in that the digital control logic is inverted. the adg811 switches are turned on with a logic low on the appropriate control input, while a logic high is required to turn on the switches of the adg812. the adg813 contains two switches whose digital control logic is similar to the adg811, while the logic is inverted on the other two switches. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. the adg813 exhibits break-before-make switching action. the adg811/adg812/adg813 are fully specified for 3.3 v, 2.5 v, and 1.8 v supply operation. the adg811 is available in a 16-lead tssop package and a 16-lead lfcsp package, and the adg812/adg813 are available in a 16-lead tssop package. functional block diagrams s1 d1 s2 d2 s3 d3 s4 d4 in1 in2 in3 in4 adg811 switches shown for a logic 1 input s1 d1 s2 d2 s3 d3 s4 d4 in1 in2 in3 in4 adg812 s1 d1 s2 d2 s3 d3 s4 d4 in1 in2 in3 in4 adg813 04306-a-001 figure 1. product highlights 1. <0.8 over full temperature range of ?40c to +125c. 2. single 1.65 v to 3.6 v operation. 3. operational with 1.8 v cmos logic. 4. high current handling capability (300 ma continuous current at 3.3 v). 5. low thd + n (0.02% typical). 6. small 3 mm 3 mm lfcsp package and 16-lead tssop package.
adg811/adg812/adg813 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagrams ............................................................. 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ............................7 ? typical performance characteristics ..............................................8 ? test circuits ..................................................................................... 11 ? terminology .................................................................................... 13 ? outline dimensions ....................................................................... 14 ? ordering guide .......................................................................... 15 ? revision history 11/09rev. a to rev. b added 16-lead lfcsp ....................................................... universal changes to table 4 ............................................................................ 6 changes to pin configurations and function description section ................................................................................................ 7 moved terminology section ......................................................... 13 updated outline dimensions ....................................................... 14 changes to ordering guide .......................................................... 15 5/04rev. 0 to rev. a updated format .................................................................. universal updated package choices ................................................. universal 11/03revision 0: initial version
adg811/adg812/adg813 rev. b | page 3 of 16 specifications v dd = 2.7 v to 3.6 v, gnd = 0 v, unless otherwise noted. temperature range for the y version is ?40c to +125c. table 1. parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 0.5 typ v dd = 2.7 v, v s = 0 v to v dd , i s = 10 ma; see figure 19 0.65 0.75 0.8 max on resistance match between channels, r on 0.04 typ v dd = 2.7 v, v s = 0.5 v, i s = 10 ma 0.075 0.08 max on resistance flatness, r flat (on) 0.1 typ v dd = 2.7 v, v s = 0 v to v dd , i s = 10 ma 0.15 0.16 max leakage currents v dd = 3.6 v source off leakage, i s (off ) 0.2 na typ v s = 0.6 v/3.3 v, v d = 3.3 v/0.6 v; see figure 20 1 8 80 na max drain off leakage, i d (off ) 0.2 na typ v s = 0.6 v/3.3 v, v d = 3.3 v/0.6 v; see figure 20 1 8 80 na max channel on leakage, i d , i s (on) 0.2 na typ v s = v d = 0.6 v or 3.3 v; see figure 21 1 15 90 na max digital inputs input high voltage, v inh 2 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 6 pf typ dynamic characteristics 1 t on 21 ns typ r l = 50 , c l = 35 pf 25 26 28 ns max v s = 1.5 v/0 v; see figure 22 t off 4 ns typ r l = 50 , c l = 35 pf 5 6 7 ns max v s = 1.5 v; see figure 22 break-before-make time delay, t bbm (adg813 only) 17 ns typ r l = 50 , c l = 35 pf 5 ns min v s1 = v s2 = 1.5 v; see figure 23 charge injection 30 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; see figure 24 off isolation ?67 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 channel-to-channel crosstalk ?90 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 total harmonic distortion (thd + n) 0.02 % r l = 32 , f = 20 hz to 20 khz, v s = 2 v p-p insertion loss ?0.05 db typ r l = 50 , c l = 5 pf, f = 100 khz ?3 db bandwidth 90 mhz typ r l = 50 , c l = 5 pf; see figure 26 c s (off ) 30 pf typ c d (off ) 35 pf typ c d , c s (on) 60 pf typ power requirements v dd = 3.6 v i dd 0.003 a typ digital inputs = 0 v or 3.6 v 1.0 4 a max 1 guaranteed by design, but not subject to production test.
adg811/adg812/adg813 rev. b | page 4 of 16 v dd = 2.5 v 0.2 v, gnd = 0 v, unless otherwise noted. temperature range for the y version is ?40c to +125c. table 2. parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 0.65 typ v dd = 2.3 v, v s = 0 v to v dd , i s = 10 ma; see figure 19 0.72 0.8 0.88 max on resistance match between channels, r on 0.04 typ v dd = 2.3 v, v s = 0.55 v, i s = 10 ma 0.08 0.085 max on resistance flatness, r flat (on) 0.16 typ v dd = 2.3 v, v s = 0 v to v dd , i s = 10 ma 0.23 0.24 max leakage currents v dd = 2.7 v source off leakage, i s (off ) 0.2 na typ v s = 0.6 v/2.4 v, v d = 2.4 v/0.6 v; see figure 20 1 6 35 na max drain off leakage, i d (off ) 0.2 na typ v s = 0.6 v/2.4 v, v d = 2.4 v/0.6 v; see figure 20 1 6 35 na max channel on leakage, i d , i s (on) 0.2 na typ v s = v d = 0.6 v or 2.4 v; see figure 21 1 11 70 na max digital inputs input high voltage, v inh 1.7 v min input low voltage, v inl 0.7 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max c in , digital input capacitance 6 pf typ dynamic characteristics 1 t on 22 ns typ r l = 50 , c l = 35 pf 27 29 30 ns max v s = 1.5 v/ 0 v; see figure 22 t off 4 ns typ r l = 50 , c l = 35 pf 6 7 8 ns max v s = 1.5 v; see figure 22 break-before-make time delay, t bbm (adg813 only) 18 ns typ r l = 50 , c l = 35 pf 5 ns min v s1 = v s2 = 1.5 v; see figure 23 charge injection 25 pc typ v s = 1.25 v, r s = 0 , c l = 1 nf; see figure 24 off isolation ?67 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 25 channel-to-channel crosstalk ?90 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 total harmonic distortion (thd + n) 0.022 % r l = 32 , f = 20 hz to 20 khz, v s = 1.5 v p-p insertion loss ?0.06 db typ r l = 50 , c l = 5 pf, f = 100 khz ?3 db bandwidth 90 mhz typ r l = 50 , c l = 5 pf; see figure 26 c s (off ) 32 pf typ c d (off ) 37 pf typ c d , c s (on) 60 pf typ power requirements v dd = 2.7 v i dd 0.003 a typ digital inputs = 0 v or 2.7 v 1.0 4 a max 1 guaranteed by design, but not subject to production test.
adg811/adg812/adg813 rev. b | page 5 of 16 v dd = 1.65 v to 1.95 v, gnd = 0 v, unless otherwise noted. temperature range for the y version is ?40c to +125c. table 3. parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 1 typ v dd = 1.8 v, v s = 0 v to v dd , i s = 10 ma; see figure 19 1.4 2.2 2.2 max 2.5 4 4 max v dd = 1.65 v, v s = 0 v to v dd , i s = 10 ma on resistance match between channels, r on 0.1 typ v dd = 1.65 v, v s = 0.7 v, i s = 10 ma leakage currents v dd = 1.95 v source off leakage i s (off ) 0.2 na typ v s = 0.6 v/1.65 v, v d = 1.65 v/0.6 v; see figure 20 1 5 30 na max drain off leakage i d (off ) 0.2 na typ v s = 0.6 v/1.65 v, v d = 1.65 v/0.6 v; see figure 20 1 5 30 na max channel on leakage i d , i s (on) 0.2 na typ v s = v d = 0.6 v or 1.65 v; see figure 21 1 9 60 na max digital inputs input high voltage, v inh 0.65v dd v min input low voltage, v inl 0.35v dd v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max cin, digital input capacitance 6 pf typ dynamic characteristics 1 t on 27 ns typ r l = 50 , c l = 35 pf 35 36 37 ns max v s = 1.5 v/ 0 v; see figure 22 t off 6 ns typ r l = 50 , c l = 35 pf 8 9 10 ns max v s = 1.5 v; see figure 22 break-before-make time delay, t bbm (adg813 only) 20 ns typ r l = 50 , c l = 35 pf 5 ns min v s1 = v s2 = 1 v; see figure 23 charge injection 15 pc typ v s = 1 v, r s = 0 , c l = 1 nf; see figure 24 off isolation ?67 db typ r l = 50 , c l = 5 pf, f = 100 khz; figure 25 channel-to-channel crosstalk ?90 db typ r l = 50 , c l = 5 pf, f = 100 khz; see figure 27 total harmonic distortion (thd + n) 0.14 % r l = 32 , f = 20 hz to 20 khz, v s = 1.2 v p-p insertion loss ?0.08 db typ r l = 50 , c l = 5 pf, f = 100 khz C3 db bandwidth 90 mhz typ r l = 50 , c l = 5 pf; see figure 26 c s (off ) 32 pf typ c d (off ) 38 pf typ c d , c s (on) 60 pf typ power requirements v dd = 1.95 v i dd 0.003 a typ digital inputs = 0 v or 1.95 v 1.0 4 a max 1 guaranteed by design, but not subject to production test.
adg811/adg812/adg813 rev. b | page 6 of 16 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +4.6 v analog inputs 1 ?0.3 v to v dd + 0.3 v digital inputs 1 gnd ? 0.3 v to 4.6 v or 10 ma, whichever occurs first peak current, s or d (pulsed at 1 ms, 10% duty-cycle maximum) 3.3 v operation 500 ma 2.5 v operation 460 ma 1.8 v operation 420 ma continuous current, s or d 3.3 v operation 300 ma 2.5 v operation 275 ma 1.8 v operation 250 ma operating temperature range, automotive (y version) ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c tssop package ja thermal impedance 150c/w jc thermal impedance 27c/w lfcsp package ja thermal impedance 70c/w ir reflow, peak temperature <20 sec 235c 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. table 5. adg811/adg812 truth table adg811 in adg812 in switch condition 0 1 on 1 0 off table 6. adg813 truth table logic switch 1, switch 4 switch 2, switch 3 0 off on 1 on off esd caution
adg811/adg812/adg813 rev. b | page 7 of 16 pin configurations and function descriptions nc = no connect nc d1 s1 in1 in4 s4 d4 gnd d2 s2 vdd in2 s3 d3 in3 nc top view (not to scale) adg811/ adg812/ adg813 4 2 3 1 8 6 7 5 15 14 13 16 11 10 9 12 04306-a-002 figure 2. adg811/adg812/adg813 pin configuration (16-lead tssop) table 7. adg811/adg812/adg813 pin configuration (16-lead tssop) pin no. mneonic definition 1 in1 logic control input. 2 d1 drain terminal. this pin may be an input or output. 3 s1 source terminal. this pin may be an input or output. 4 nc no connect. 5 gnd ground (0 v) reference. 6 s4 source terminal. this pin may be an input or output. 7 d4 drain terminal. this pin may be an input or output. 8 in4 logic control input. 9 in3 logic control input. 10 d3 drain terminal. this pin may be an input or output. 11 s3 source terminal. this pin may be an input or output. 12 nc no connect. 13 vdd most positive power supply potential. 14 s2 source terminal. this pin may be an input or output. 15 d2 drain terminal. this pin may be an input or output. 16 in2 logic control input. 04306-027 pin 1 indicator notes 1. nc = no connect. 2. connect exposed pad to gnd. 1 s1 2 nc 3 gnd 4 s4 11 vdd 12 s2 10 nc 9s3 5 d4 6 in4 7 in3 8 d3 15 in1 16 d1 14 in2 13 d2 adg811 top view (not to scale) figure 3. adg811 pin conf iguration (16-lead lfcsp) table 8. adg811 pin configuration (16-lead lfcsp) pin no. mneonic definition 1 s1 source terminal. this pin may be an input or output. 2 nc no connect. 3 gnd ground (0 v) reference. 4 s4 source terminal. this pin may be an input or output. 5 d4 drain terminal. this pin may be an input or output. 6 in4 logic control input. 7 in3 logic control input. 8 d3 drain terminal. this pin may be an input or output. 9 s3 source terminal. this pin may be an input or output. 10 nc no connect. 11 vdd most positive power supply potential. 12 s2 source terminal. this pin may be an input or output. 13 d2 drain terminal. this pin may be an input or output. 14 in2 logic control input. 15 in1 logic control input. 16 d1 drain terminal. this pin may be an input or output. epad connect exposed pad to gnd.
adg811/adg812/adg813 rev. b | page 8 of 16 typical performance characteristics 0.60 0.55 0.50 0.45 on resistance ( ) 0.40 0.35 0.30 0.25 0.20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v d , v s (v) v dd = 2.7v v dd = 3v t a = 25c v dd = 3.6v v dd = 3.3v 04306-a-003 figure 4. on resistance vs. v d (v s ), v dd = 2.7 v to 3.6 v v d , v s (v) on resistance ( ) 04306-a-004 0.8 0.3 0.4 0.5 0.6 0.7 0.2 0 0.5 2.5 2.0 1.5 1.0 t a = 25c v dd = 2.3v v dd = 2.5v v dd = 2.7v figure 5. on resistance vs. v d (v s ), v dd = 2.5 v 0.2 v v d , v s (v) on resistance ( ) 04306-a-005 1.8 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 t a = 25c v dd = 1.8v v dd = 1.65v v dd = 1.95v figure 6. on resistance vs. v d (v s ), v dd = 1.8 v 0.15 v v d , v s (v) on resistance ( ) 04306-a-006 1.2 0.2 0.4 0.6 0.8 1.0 0 0 3.0 2.5 2.0 1.5 1.0 0.5 +125c +85c +25c ?40c v dd = 3.3v figure 7. on resistance vs. v d (v s ) for different temperatures, v dd = 3.3 v v d , v s (v) on resistance ( ) 04306-a-007 1.2 0.2 0.4 0.6 0.8 1.0 0 0 2.5 2.0 1.5 1.0 0.5 +125c +25c v dd = 2.5v +85c ?40c figure 8. on resistance vs. v d (v s ) for different temperatures, v dd = 2.5 v v d , v s (v) on resistance ( ) 04306-a-008 1.4 0.2 0.4 0.6 0.8 1.0 1.2 0 0 1.8 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 +25c ?40c +85c +125c v dd = 1.8v figure 9. on resistance vs. v d (v s ) for different temperatures, v dd = 1.8 v
adg811/adg812/adg813 rev. b | page 9 of 16 temperature (c) current (na) 04306-a-009 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 120 100 80 60 40 20 0 140 i d (off) i d , i s (on) v dd = 3.3v i s (off) figure 10. leakage current vs. temperature, v dd = 3.3 v temperature (c) current (na) 04306-a-010 ?60 ?50 ?40 ?30 ?20 ?10 0 10 i d , i s (on) v dd = 2.5v i s (off) i d (off) 120 100 80 60 40 20 0 140 figure 11. leakage current vs. temperature, v dd = 2.5 v temperature (c) current (na) 04306-a-011 ?60 ?50 ?40 ?30 ?20 ?10 0 i d , i s (on) i s (off) i d (off) v dd = 1.8v 120 100 80 60 40 20 0 140 figure 12. leakage current vs. temperature, v dd = 1.8 v v s (v) q inj (pc) 04306-a-012 0 20 40 60 80 100 120 2.5 2.0 1.0 1.5 0 0.5 3.0 3.5 4.0 t a = 25c v cc = 2.5v v cc = 3.6v v cc = 1.8v figure 13. charge injection (q inj ) vs. source voltage (v s ) temperature (c) time (ns) 04306-a-013 0 5 10 15 20 25 30 35 t off t on v cc = 3v v cc = 3v v dd = 2.5v v dd = 1.8v v cc = 2.5v v cc = 1.8v 60 80 100 120 4020 ?20 ?40 0 figure 14. t on /t off times vs. temperature frequency (mhz) attenuation (db) 04306-a-014 ?10 ?8 ?4 ?2 0 1 ?6 ?9 ?5 ?3 ?1 ?7 0.01 0.1 1000 100 10 1 v cc = 3.3v/2.5v/1.8v t a = 25c figure 15. on response vs. frequency
adg811/adg812/adg813 rev. b | page 10 of 16 frequency (mhz) attenuation (db) 04306-a-015 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.01 0.1 1000 100 10 1 v cc = 3.3v/2.5v/1.8v t a = 25c figure 16. crosstalk vs. frequency frequency (mhz) attenuation (db) 04306-a-016 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.01 0.1 1000 100 10 1 v cc = 3.3v/2.5v/1.8v t a = 25c figure 17. off isol ation vs. frequency frequency (hz) thd+n (%) 04306-a-017 0.02 0.04 0.05 0.06 0.08 v dd = 2.5v t a = 25c 32 load 1.5v p-p 20 50 100 200 500 1k 2k 5k 10k 20k figure 18. total harmonic distortion + noise (thd + n) vs. frequency
adg811/adg812/adg813 rev. b | page 11 of 16 test circuits v s r on = v1/i ds i ds v1 04306-a-018 sd figure 19. on resistance v s v d i s (off) i d (off) a a sd 04306-a-019 figure 20. off leakage v d i d (on) nc sd a 04306-a-020 figure 21. on leakage sd in gnd r l 50 c l 35pf v dd v in v out v in v out v s v dd t on t off 50% 50% 90% 90% 50% 50% 0.1 f adg811 adg812 04306-a-021 figure 22. switching times in1, in2 s1 d1 0.1 f gnd r l2 50 r l1 50 s2 d2 v dd v out2 v out1 v s1 v s2 v in v dd c l1 35pf c l2 35pf v out v in t bbm t bbm 50% 50% 80% 0v 80% 04306-a-022 figure 23. break-before-make time delay, t bbm (adg813 only) in gnd c l 1nf v dd sd r s v s v in v out v out v dd sw on q inj = c l v out sw off v out 04306-a-023 figure 24. charge injection
adg811/adg812/adg813 rev. b | page 12 of 16 network analyzer r l gnd v dd v dd v dd v s s 0.1 f d 50 50 50 off isolation = 20 log v s v out 04306-a-024 figure 25. off isolation network analyzer r l gnd v dd v dd v dd v s s 0.1 f d 50 50 insertion loss = 20 log v out with switch v out without switch 04306-a-025 figure 26. bandwidth r l gnd v dd v dd v out v s s1 s2 0.1 f d 50 r l 50 50 channel-to-channel crosstalk = 20 lo g v out v s network analyzer 04306-a-026 figure 27. channel-to-channel crosstalk
adg811/adg812/adg813 rev. b | page 13 of 16 terminology i dd positive supply current. v d , v s analog voltage on terminal d, terminal s. r on ohmic resistance between d and s. r flat (on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. r on on resistance match between any two channels, that is, r on maximum ? r on minimum. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d , c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on delay time between the 50% and the 90% points of the digital input and switch on condition. t off delay time between the 50% and the 90% points of the digital input and switch off condition. t bbm on or off time measured between the 80% points of both switches, when switching from one to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during on-to-off switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another because of parasitic capacitance. ?3 db bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. thd + n the ratio of the harmonic amplitudes plus noise of a signal to the fundamental.
adg811/adg812/adg813 rev. b | page 14 of 16 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 28. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 1 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.45 1.30 sq 1.15 exposed pad 16 5 13 8 9 12 4 (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. 072208-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 29. 16-lead lead frame chip scale package [lfcsp_vq] 3 mm 3 mm body, very thin quad (cp-16-2) dimensions shown in millimeters
adg811/adg812/adg813 rev. b | page 15 of 16 ordering guide model temperature range packag e description package option adg811yru C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 adg811yru-reel C40c to +125c 16-lead th in shrink small outline [tssop] ru-16 adg811yru-reel7 C40c to +125c 16-lead th in shrink small outline [tssop] ru-16 adg811yruz 1 C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 adg811ycpz-reel 1 C40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-2 adg811ycpz-reel7 1 C40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-2 adg812yru C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 adg812yru-reel C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 adg812yru-reel7 C40c to +125c 16-lead th in shrink small outline [tssop] ru-16 ADG812YRUZ 1 C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 ADG812YRUZ-reel7 1 C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 adg813yru C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 adg813yru-reel C40c to +125c 16-lead th in shrink small outline [tssop] ru-16 adg813yru-reel7 C40c to +125c 16-lead th in shrink small outline [tssop] ru-16 adg813yruz 1 C40c to +125c 16-lead thin shrink small outline [tssop] ru-16 1 z = rohs compliant part.
adg811/adg812/adg813 rev. b | page 16 of 16 notes ?2003C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d04306-0-11/09(b)

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